1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and more particularly to a cross-sectional configuration of an element-to-element line for electrically connecting semiconductor elements to each other.
2. Description of the Background Art
FIG. 56 is a cross-sectional view of an inner portion of a conventional semiconductor integrated circuit device. Semiconductor elements 2 and 3 are formed on the surface of a semiconductor substrate 1, as shown in FIG. 56. The semiconductor element 2 is a transistor including diffusion regions 101, 102, an insulating film 103 and a gate electrode 104, and the semiconductor element 3 is a diffused resistor including a diffusion region 105. The semiconductor elements 2 and 3 are connected electrically to each other with an element-to-element line 4, as shown. Reference numeral 5 designates a protective film, and 6 to 9 designate other lines.
As above described, the semiconductor elements 2 and 3 are formed on the semiconductor substrate 1, and the element-to-element line is formed for electrically connecting the semiconductor elements, to provide the semiconductor integrated circuit device.
FIG. 57 is a cross-sectional view taken along the line A--A of FIG. 56. The ordinary element-to-element line 4 is of a quadrangular (rectangular) configuration configuration in cross section having horizontal portions at its upper and lower surfaces, as shown in FIG. 57.
FIG. 58 schematically illustrates parasitic capacitances generated by forming lines. An adjacent line-to-line parasitic capacitance C1 is generated between adjacent lines 41 and 42, an adjacent line-to-line parasitic capacitance C2 is generated between adjacent lines 42 and 43, and a substrate-to-line parasitic capacitance C3 is generated between the line 42 and the semiconductor substrate 1.
The parasitic capacitances have not presented a serious problem in the prior art semiconductor manufacturing technique because of its large design size. However, as recent rapid advance of the manufacturing technique has caused the design size to be finer, the parasitic capacitances due to two-dimensional size of lines have not been negligible compared with capacitances of materials.
Consequently, the increase in the parasitic capacitances due to the line formation causes a reduction in operating speeds of the semiconductor integrated circuit device and an increase in power consumption.